(1) Field of the Invention
This invention relates to a nonvolatile semiconductor memory, a method for reading such a nonvolatile semiconductor memory, and a microprocessor and, more particularly, to an electrically erasable programmable virtual ground nonvolatile semiconductor memory, a method for reading such a nonvolatile semiconductor memory, and a microprocessor including such a nonvolatile semiconductor memory.
(2) Description of the Related Art
Conventionally, floating gate virtual ground nonvolatile semiconductor memories have widely been used as electrically erasable programmable nonvolatile semiconductor memories.
FIG. 7 is a view showing the structure of a conventional floating gate virtual ground AND-type nonvolatile semiconductor memory.
A memory cell array of a floating gate virtual ground nonvolatile semiconductor memory includes floating gate nonvolatile memory cells (memory cells) m11, m12, etc. arranged like a matrix, word lines WL1, WL2, etc. arranged in the direction of each row of memory cells, and bit lines BL1, BL2, etc. arranged in the direction of each column of memory cells. Each of the word lines WL1, WL2, etc. is connected to gate electrodes of memory cells arranged in a row. The bit lines BL1, BL2, etc. are connected to a read conversion circuit SA0 which is used for reading out data and which is also connected to a reference cell mR.
In a data read process, a threshold of a storage area in a memory cell is read out, the threshold is compared with a reference value, and the threshold is converted into data according to whether the threshold is higher or lower than the reference value. When the threshold is read out, voltages VWL and VBL are applied to a word line and a bit line, respectively, corresponding to a selected address. For example, to read out a threshold of the memory cell m24 connected to the word line WL2 and the bit lines BL4 and BL5, the voltage VWL is applied to the word line WL2 and the voltage VBL is applied to the bit line BL4. The bit line BL5 which is adjacent to the bit line BL4 with the memory cell m24 between is connected to GND. As a result, a drain current Id0 varies according to the number of electrons stored in a floating gate of the memory cell m24. Similarly, voltages VWL and VBL are applied to a word line WLR and a bit line BLR, respectively, of the reference cell mR and GND is applied to an opposite source line. On the basis of whether the drain current Id0 which runs through the memory cell m24 is more or less powerful than a drain current IdR which runs through the reference cell mR, the read conversion circuit SA0 determines which of “0” and “1” it should output, and outputs data output DO0.
A virtual ground semiconductor memory in which two different memory cells between which a non-selected memory cell is are read at the same time is proposed (see, for example, Japanese Patent Laid-Open Publication No. Hei 7-57487 (Paragraphs [0009]-[0011] and FIG. 1)). With this virtual ground semiconductor memory, a leakage current that runs through the non-selected memory cell is decreased by performing such reading. As a result, power consumption decreases.
With floating gate virtual ground nonvolatile semiconductor memories, however, it is difficult to perform high-speed reading.
With the conventional floating gate virtual ground nonvolatile semiconductor memory, the read conversion circuit SA0 determines on the basis of a comparison between the drain current which runs through the memory cell and the drain which runs through the reference cell whether output is “0” or “1”. Therefore, unless there is a sufficiently great difference between the drain current which runs through the memory cell and the drain current which runs through the reference cell, the read conversion circuit SA0 cannot make a determination. To make a determination, these drain currents should be amplified. However, time necessary for the stabilization of a value is proportional to an amplification factor, resulting in a slow read rate. Furthermore, the drain current flows through the memory cell and to GND. However, a current Idleak also flows to a non-selected memory cell. Accordingly, with the conventional floating gate virtual ground nonvolatile semiconductor memory it is difficult to perform high-speed reading. In addition, the reference cell for generating the drain current for comparison is essential to determination made by the read conversion circuit SA0. Accordingly, memory cell array area for the reference cell is necessary.
On the other hand, if two bit lines “bit” and “bit/” are used and currents which run through the bit lines are compared, then a reference cell is unnecessary. If two different memory cells between which a non-selected memory cell is used, column lines outside the two different memory cells are connected to GND and bit lines inside the two different memory cells are used as “bit” and “bit/”, accordingly, currents do not flow to the outside of the column lines connected to GND and an improvement in a read rate can be expected. However, if this method is applied to the conventional floating gate virtual ground nonvolatile semiconductor memory, two memory cells are necessary for storing one bit. As a result, memory cell array area increases.